This application is based upon and claims priority from prior French Patent Application No. 0016174, filed on Dec. 12, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The invention related to integrated circuits and more particularly to semiconductor memory devices and especially, although not exclusively, to so-called xe2x80x9cembeddedxe2x80x9d memories, which are implemented conjointly with other components by the same technological process, for example, and intended to be integrated together into an application-specific integrated circuit (ASIC).
2. Description of the Prior Art
Dynamic random access memories (DRAM) represent close to two thirds of worldwide memory production. At present, in the integration race, there a two dominant architectures, known to those of ordinary skill in the art by the names xe2x80x9ctrench cellsxe2x80x9d and xe2x80x9cstacked cellsxe2x80x9d.
In a trench cells architecture the memory capacitor is implemented by a trench formed in the substrate alongside the memory point access transistor.
In a stacked cells architecture the memory capacitor is implemented on top of the access transistor and projects slightly from it.
Although technologically complex, these two architectures are easier to apply to integrated circuits including only memories, and are difficult to integrate as embedded memories in integrated circuits, especially in CMOS integrated circuits.
Memories available off the shelf include read-only memories and in particular electrically-programmable read-only memories (EPROM). These memories have the advantage of a more compact overall size than a DRAM, but the drawback of a longer read time than a DRAM.
On the other hand, a DRAM has a shorter read and write time than an EPROM, but its overall size is larger.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above, and in particular for providing a memory device that is small in size while fast in operation.
The invention aims to propose a new integrated semiconductor memory device that combines the advantage of small overall size, like that of an EPROM, with a read and write time comparable to that of a DRAM, i.e. faster than an EPROM.
A preferred embodiment of the present invention therefore proposes an integrated semiconductor memory device including at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. The device also includes biasing means adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.
One benefit of the proposed structure is that the quantity of charge stored is very small, which eliminates the need for a dedicated storage capacitor. The read sensitivity is not destroyed however, thanks to using the gain of the transistor in the read process. The structure according to the invention therefore has the advantage of a charge storage area under the access transistor with a very short read and write time, and accordingly has integration and density capabilities improved over the architectures of memories currently in production.
What is more, the greater sensitivity of the new structure also predisposes it to opto-electronic applications, for example in image sensors, light detectors or opto-electronic components.
Unlike EPROM structures, the barrier that traps the charges is a quantum well, rather than a layer of oxide, which means that the process of charging and discharging the memory according to the invention does not require the passage of a current through an oxide. This is particularly advantageous from the point of view of speed and the reliability of the memory structure according to the invention.
In one embodiment of the invention, the substrate is formed of a first semiconductor material having a first type of conductivity. The first material can be P-doped silicon, for example if the memory is an NMOS structure. The quantum well area is formed of a buried semiconductor layer and composed of a second semiconductor material having the first type of conductivity and a gap between the valency band and the conduction band smaller than the corresponding gap of the first material.
The second material can be a silicon-germanium alloy, for example. The memory point structure also includes buried insulative regions extending laterally between said buried semiconductor layer (the quantum well) and the source and drain regions of the transistor. The memory point structure also includes a channel region of the transistor situated in the upper part of the substrate above the buried semiconductor layer, and weakly doped source and drain extension areas (NLDD areas in the case of an NMOS structure) extending between the channel region and the source and drain regions and over at least part of the buried insulative regions.
In this regard, it is preferable for the length of the quantum well area to be substantially equal to the length of the gate. This is because, the shorter the quantum well area, the less memory effect the structure will have. Conversely, the larger the quantum well area, the higher the risk of recombination of carriers between the quantum well area and the source and drain extension areas.
One of ordinary skill in the art will naturally know how to adjust the length of the quantum well area to suit the intended application.
When the first material is silicon and the second material is a silicon-germanium alloy, the percentage of germanium affects the height of the barrier xe2x80x9cseenxe2x80x9d by the carriers trapped in the quantum well and the connection of the lattices with the silicon during the epitaxial growth process used in the fabrication of the device according to the invention.
To be more precise, the lower the percentage of germanium, the lower the barrier seen by carriers trapped in the quantum well.
Also, the higher the percentage of germanium, the more problematical the linking of the silicon-germanium lattice with the silicon lattice will be during epitaxial growth.
In other words, the higher the percentage of germanium, the greater the risk of relaxation of the silicon-germanium, causing the appearance of dislocations in the silicon, and possibly leading to non-functioning of the memory.
Once again, one of ordinary skill in the art will know how to adjust the percentage of germanium to be used, in particular as a function of the thickness of the material. For example, a percentage of germanium less than or equal to 50% and greater than or equal to 20% would be chosen for a thickness of the order of 10 nanometers. The percentage of germanium could be increased for smaller thicknesses.
The doping of the quantum well area also affects the behavior of the memory point structure. The higher the doping of the quantum well area, the higher the barrier. Conversely, the lower the doping of the quantum well area, the lower the barrier, leading to a shorter charge confinement time, and consequently a faster loss of the memory effect.
The doping used depends on the intended application. For example, the quantum well area can be doped to a concentration from 1017 at/cm3 to 1020 at/cm3.
Similarly, the doping of the substrate is advantageously chosen to be sufficient to enable operation of the transistor. It is also preferable for the doping not to be too high. In the area of the conduction channel of the transistor (in the upper part of the substrate), doping that is too high can modify the drain current due to the presence of confined holes, while in the area of the substrate (in the lower part of the substrate), doping that is too high affects the curvature of the valency band and consequently the tendency of the charges to be evacuated.
For example, the substrate is preferably doped to a concentration less than or equal to 1019 at/cm3 and greater than 1015 at/cm3.